View EDI88257CA_371876.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

EDI88257CA
HI-RELIABILITY PRODUCT
256Kx8 Monolithic SRAM
FEATURES
s Access Times of 20, 25, 35, 45, 55ns s Data Retention Function (LPA Versions) s TTL Compatible Inputs and Outputs s Fully Static, No Clocks s Organized as 256Kx8 s Commercial, Industrial and Military Temperature Ranges s JEDEC Approved Evolutionary Pinout * 32 pin Ceramic DIP, 0.6 mils wide (Package 9) s Single +5V (10%) Supply Operation The EDI88257CA is a 2 Megabit 256Kx8 bit Monolithic CMOS Static RAM. The 32 pin DIP pinout adheres to the JEDEC evolutionary standard for the two megabit device. The device is upgradeable to the 512Kx8 SRAM, the EDI88512CA. Pin 1 becomes the higher order address. A Low Power version, EDI88257LPA, offers a data retention function for battery back-up opperation. Military product is available compliant to Appendix A of MIL-PRF-38535.
FIG. 1
PIN CONFIGURATION PIN DESCRIPTION
32 DIP
I/O0-7 A0-17
32 VCC 31 A15 30 A17 29 WE 28 A13 27 A8 26 A9 25 A11 24 OE 23 A10 22 CS 21 I/O7 20 I/O6 19 I/O5 18 I/O4 17 I/O3
AO-17
TOP VIEW
NC A16 A14 A12 A7 A6 A5 A4 A3 A2 A1 AO I/OO I/O1 I/O2 VSS 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
Data Inputs/Outputs Address Inputs Write Enable Chip Selects Output Enable Power (+5V 10%) Ground Not Connected
WE CS OE VCC VSS
BLOCK DIAGRAM
Memory Array
NC
Address Buffer
Address Decoder
I/O Circuits
I/OO-7
WE CS OE
May 2000 Rev. 2
1
White Electronic Designs Corporation * (602) 437-1520 * www.whiteedc.com
EDI88257CA
ABSOLUTE MAXIMUM RATINGS
Parameter Voltage on any pin relative to Vss Operating Temperature TA (Ambient) Industrial Military Storage Temperature, Ceramic Power Dissipation Output Current Junction Temperature, TJ -40 to +85 -55 to +125 -65 to +150 1.5 20 175 C C C W mA C -0.5 to 7.0 Unit V OE X H L X CS H L L L WE X H H L
TRUTH TABLE
Mode Standby Output Deselect Read Write Output High Z High Z Data Out Data In Power Icc2, Icc3 Icc1 Icc1 Icc1
RECOMMENDED OPERATING CONDITIONS
Parameter Supply Voltage Supply Voltage Input High Voltage Input Low Voltage Symbol VCC VSS VIH VIL Min 4.5 0 2.2 -0.3 Typ 5.0 0 -- -- Max 5.5 0 Vcc +0.5 +0.8 Unit V V V V
NOTE: Stress greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions greater than those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.
CAPACITANCE (TA = +25C)
Parameter Address Lines Input/Output Lines Symbol CI CO Condition VIN = Vcc or Vss, f = 1.0MHz VOUT = Vcc or Vss, f = 1.0MHz Max 12 14 Unit pF pF
These parameters are sampled, not 100% tested.
DC CHARACTERISTICS (VCC = 5V, TA = +25C)
Parameter Input Leakage Current Output Leakage Current Operating Power Supply Current Standby (TTL) Power Supply Current Full Standby Power Supply Current Output Low Voltage Output High Voltage Symbol ILI ILO ICC1 ICC2 ICC3 VOL VOH VIN = 0V to VCC VI/O = 0V to VCC WE, CS = VIL, II/O = 0mA, Min Cycle CS VIH, VIN VIL, VIN VIH CS VCC -0.2V VIN Vcc -0.2V or VIN 0.2V IOL = 8.0mA IOH = -4.0mA CA LPA (20-25ns) (35-55ns) Conditions Min -10 -10 -- -- -- -- -- -- 2.4 -- -- -- -- Typ -- -- Max +10 +10 225 200 60 25 20 0.4 -- A A mA mA mA mA mA V V Units
NOTE: DC test conditions: VIL = 0.3V, VIH = Vcc -0.3V
White Electronic Designs Corporation * (602) 437-1520 * www.whiteedc.com
2
EDI88257CA
AC CHARACTERISTICS - READ CYCLE (VCC = 5.0V, VSS = 0V, TA = -55C to +125C))
Parameter Read Cycle Time Address Access Time Chip Select Access Time Chip Select to Output in Low Z (1) Chip Disable to Output in High Z (1) Output Hold from Address Change Output Enable to Output Valid Output Enable to Output in Low Z (1) Output Disable to Output in High Z (1) Symbol JEDEC Alt. tAVAV tAVQV tELQV tELQX tEHQZ tAVQX tGLQV tGLQX tGHQZ tRC tAA tACS tCLZ tCHZ tOH tOE tOLZ tOHZ 0 0 8 3 0 0 10 0 0 10 8 20ns Min Max 20 20 20 3 0 0 12 0 0 15 10 25ns Min 25 25 25 3 0 0 15 0 0 20 15 Max 35ns Min Max 35 35 35 3 0 0 25 0 0 20 20 45ns Min Max 45 45 45 3 0 0 25 20 55ns Min Max 55 55 55 Units ns ns ns ns ns ns ns ns ns
1. This parameter is guaranteed by design but not tested.
AC CHARACTERISTICS - WRITE CYCLE (VCC = 5.0V, VSS = 0V, TA = -55C to +125C)
Parameter Write Cycle Time Chip Select to End of Write Address Setup Time Address Valid to End of Write Write Pulse Width Write Recovery Time Data Hold Time Write to Output in High Z (1) Data to Write Time Output Active from End of Write (1) Symbol JEDEC Alt. tAVAV tELWH tELEH tAVWL tAVEL tAVWH tAVEH tWLWH tWLEH tWHAX tEHAX tWHDX tEHDX tWLQZ tDVWH tDVEH tWHQX tWC tCW tCW tAS tAS tAW tAW tWP tWP tWR tWR tDH tDH tWHZ tDW tDW tWLZ 20ns Min Max 20 15 15 0 0 15 15 15 15 0 0 0 0 0 10 10 0 8 Min 25 17 17 0 0 17 17 17 17 0 0 0 0 0 12 12 0 10 25ns Max 35ns Min Max 35 25 25 0 0 25 25 25 25 0 0 0 0 0 20 20 0 25 45ns Min Max 45 30 30 0 0 30 30 30 30 0 0 0 0 0 25 25 0 30 55ns Min Max 45 30 30 0 0 30 30 30 30 0 0 0 0 0 25 25 0 30 Units ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
1. This parameter is guaranteed by design but not tested.
AC TEST CONDITIONS
Figure 1
Vcc
Figure 2
Vcc
480
480
Input Pulse Levels Input Rise and Fall Times Input and Output Timing Levels Output Load
VSS to 3.0V 5ns 1.5V Figure 1
NOTE: For tEHQZ, tGHQZ and tWLQZ, CL = 5pF Figure 2)
Q 255 30pF Q 255 5pF
3
White Electronic Designs Corporation * (602) 437-1520 * www.whiteedc.com
EDI88257CA
FIG. 2
TIMING WAVEFORM - READ CYCLE
ADDRESS
tAVAV tAVQV
tAVAV
ADDRESS
ADDRESS 1 ADDRESS 2
CS
tELQV tELQX
OE
tEHQZ
tAVQV
DATA I/O
tAVQX
DATA 1 DATA 2
tGLQV tGLQX
DATA OUT
tGHQZ
READ CYCLE 1 (WE HIGH; OE, CS LOW)
READ CYCLE 2 (WE HIGH)
FIG. 3
WRITE CYCLE - WE CONTROLLED
tAVAV
ADDRESS
tAVWH tELWH
CS
tWHAX
tAVWL
WE
tWLWH tDVWH tWHDX
DATA IN
DATA VALID
tWLQZ
DATA OUT
HIGH Z
tWHQX
WRITE CYCLE 1, WE CONTROLLED
FIG. 4
WRITE CYCLE - CS CONTROLLED
ADDRESS
tAVAV
WS32K32-XHX
tAVEH tELEH tEHAX tAVEL tWLEH tDVEH tEHDX
CS
WE
DATA IN DATA OUT
HIGH Z
DATA VALID
WRITE CYCLE 2, CS CONTROLLED
White Electronic Designs Corporation * (602) 437-1520 * www.whiteedc.com
4
EDI88257CA
DATA RETENTION CHARACTERISTICS (EDI88257LPA ONLY) (TA = -55C to +125C)
Characteristic Low Power Version only Data Retention Voltage Data Retention Quiescent Current Chip Disable to Data Retention Time Operation Recovery Time Sym VDD ICCDR TCDR TR Conditions VDD = 2.0V CS VDD -0.2V VIN VDD -0.2V or VIN 0.2V Min 2 - 0 TAVAV Typ - - - - Max - 2 - - Units V mA ns ns
FIG. 5
DATA RETENTION - CS CONTROLLED
Data Retention Mode
Vcc
4.5V VDD
WS32K32-XHX
4.5V
tCDR
CS
CS = VDD -0.2V
tR
DATA RETENTION, CS CONTROLLED
5
White Electronic Designs Corporation * (602) 437-1520 * www.whiteedc.com
EDI88257CA
PACKAGE 9:
32 PIN SIDEBRAZED CERAMIC DIP (600mils wide)
1.616 1.584
Pin 1 Indicator 0.175 0.125 0.061 0.017 0.020 0.016 15 x 0.100 = 1.500
0.060 0.040
0.620 0.600
0.100 TYP
0.155 0.115
0.600 NOM
ALL DIMENSIONS ARE IN INCHES
ORDERING INFORMATION EDI 8 8 257 CA X X X
WHITE ELECTRONIC DESIGNS SRAM ORGANIZATION, 256Kx8 TECHNOLOGY: CA = CMOS Standard Power LPA = Low Power ACCESS TIME (ns) PACKAGE TYPE: C = 32 lead Sidebrazed DIP, 600 mil (Package 9) DEVICE GRADE: B = MIL-STD-883 Compliant M = Military Screened -55C to +125C I = Industrial -40C to +85C C = Commercial 0C to +70C
White Electronic Designs Corporation * (602) 437-1520 * www.whiteedc.com
6

▲Up To Search▲

Price & Availability of EDI88257CA

	To Download EDI88257CA Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .